1. Field of the Invention
The present invention relates generally to gate array system semiconductor integrated circuit devices and particularly to gate array system semiconductor integrated circuit devices enabling mounting of a digital circuit and an analog circuit on a common chip.
2. Description of the Background Art
FIG. 5 is a plan view of a chip of a gate array system including a conventional complementary metal oxide semiconductor. Referring to FIG. 5, the chip of the gate array system including the complementary metal semiconductor (hereinafter referred to as CMOS) includes input/output buffer regions 11, and a basic cell array region 12. The input/output buffer regions 11 interface, with circuits external to the chip, a circuit formed by wiring on the basic cell array region 12. The basic cell array region 12 includes an NMOS transistor array 3 where a plurality of N channel MOS field effect transistors (hereinafter referred to as NMOS transistors) are arranged in rows; and a PMOS transistor array 4 where a plurality of PMOS transistors are arranged in rows. A basic cell is formed by an NMOS transistor and a PMOS transistor adjacent to each other in the basic cell array 12.
FIG. 6 is an enlarged view of the region B surrounded by broken lines in FIG. 5. Referring to FIG. 6, the region B includes NMOS transistor regions 3, PMOS transistor regions 4, oxide film regions 51 isolating corresponding NMOS transistor region 3 and PMOS transistor region 4, oxide film regions 52 for isolation between the NMOS transistor regions 4, and between the PMOS transistor regions 3, and well terminal regions 101, 102 formed between the oxide film regions 52. The reference numeral 1 indicates an N well region, and the reference numeral 2 indicates a P well region. The structures of the N well region 1 and P well region 2 will be described afterwards.
FIGS. 7 and 8 are sectional views taken along the line b--b' and the line c--c' in the region B of FIG. 6. Referring to FIG. 7, the NMOS transistor region 3 includes: a P well region 2 formed by injecting P type impurity (such as boron) into an N type substrate 6; a plurality of N.sup.+ diffusion layers 7 having a high N type impurity concentration formed in wells of the P well region 2; gate oxide films 8 formed on the respective N.sup.+ diffusion layers 7; and gate electrodes 9 formed on the respective gate oxide films 8. Thus, one of the N.sup.+ diffusion layers 7 opposite to each other with respect to the gate electrode 9 is a drain and the other is a source, whereby the NMOS transistor region 3 is formed.
Referring to FIG. 8, the PMOS transistor region 4 includes: an N well region 1 formed by injecting N type impurity (such as phosphorus) into the N type substrate 6; a plurality of P.sup.+ diffusion layers 7' having a high P type impurity concentration formed on the N well region 1; and gate oxide films 8 and gate electrodes 9 formed on the respective P.sup.+ diffusion layers 7'. Thus, the PMOS transistor region 4 is formed.
FIGS. 9 and 10 are sectional views taken along the lines x--x' and y--y' in FIG. 6. Referring to FIG. 9, a well terminal region 101 is formed between N channel transistor regions and it contains P type impurity. A well terminal region 102 is formed between adjacent P channel transistor regions and it contains N type impurity. The well terminal regions 101, 102 are used to connect a power supply line and a ground line formed on the P well region 2 and the N well region 1. An oxide film region 51 is formed between the NMOS transistor region 3 and PMOS transistor region 4. This oxide film region 51 isolates the NMOS transistor region 3 and the PMOS transistor region 4 from each other. An oxide film region 52 is formed between the diffusion layer 7 and the well terminal 101, and between the diffusion layer 7' and the well terminal region 102.
FIG. 11 is a diagram showing a semiconductor integrated circuit where an analog circuit and a digital circuit are mounted by wirings on prescribed portions of the gate array system chip described with reference to FIGS. 5 to 10. Referring to FIG. 11, wirings formed on this chip include a ground wiring 15, a power supply wiring 16, signal lines 181 to 188 connected to gates, drains and sources of prescribed MOS transistors, and a wiring 191 formed on the signal line 182 and connecting the drains of the NMOS transistors and the power supply wiring 16. The signal line 188 and the wiring 191 are connected by a through hole 22. The ground wiring 15 and the well terminal 101, and the power supply wiring 16 and the well terminal 102 are connected by contact holes. The MOS transistors having the gates connected to the ground wiring 15 and the power supply wiring 16 through contact holes are reversely biased, whereby the MOS transistors on both sides of the reversely biased MOS transistors are isolated.
FIG. 12 is a circuit diagram of a semiconductor integrated circuit to which the wirings in FIG. 11 are applied. Referring to FIG. 12, the analog circuit is a circuit which compares levels of input signals VI1 and VI2, and provides an output of comparison, and it is shown on the left side from the chain line in FIG. 12. The digital circuit is an inverter circuit on the right side from the chain line.
In order to operate the analog circuit shown in FIG. 12 with high precision, it is necessary to connect well terminals of NMOS transistors Tr1, Tr2, Tr3 to the sources of the respective transistors as shown in FIG. 13. However, as described above, generally in the semiconductor integrated circuit device of the CMOS gate array system, the well terminal regions 102 of the PMOS transistors are connected to the power supply wiring 16 through the contact holes, and the well terminal regions 101 of the NMOS transistors are connected to the ground wiring 15. Thus, the well terminals of the NMOS transistors are uniformly set to the ground potential and, in consequence, when the sources and the well terminals are connected, the potential of the sources are caused to be at the ground potential.
For this reason, in the semiconductor integrated circuit device of the gate array system provided with the analog circuit and the digital circuit, the analog circuit is a circuit having a low precision as shown in FIG. 12.